View MSM66507_8231468.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/24 ? semiconductor MSM66507/66p507 ? semiconductor MSM66507/66p507 olms-66k series 16-bit microcontroller general description the MSM66507/66p507 is a high-performance 16-bit microcontroller that employs oki original nx- 8/500 cpu core. the MSM66507/66p507 includes a 16-bit cpu, rom, ram, a 10-bit a/d converter, serial ports, flexible timers, a pulse-width modulator (pwm), and i/o ports. features ? program memory space : 64k bytes internal rom : 48k bytes ? data memory space : 64k bytes internal ram : 1.5k bytes ? high-speed execution minimum instruction execution time : 167ns (@24mhz) ? powerful instruction set : instruction set superior in orthogonal matrix 8/16-bit data transfer instructions 8/16-bit arithmetic instructions multiplication and division operation instructions bit manipulation instructions bit logic operation instructions rom table reference instructions ? abundant addressing modes : register addressing page addressing pointing register indirect addressing stack addressing immediate value addressing ? i/o port analog input port : 1 port 10 bits input-output port : 7 ports 8 bits, 1 port 3 bits (each bit can be assigned to input or output.) ? flexible timers free run counters : 19-bit 1, 16-bit 1 19-bit cap with a divider : 4 16-bit double buffer rto : 4 16-bit rto/pwm : 2 16-bit cap/rto : 2 ? 8-bit general timer : 1 8-bit event counter : 1 ? 16-bit pwm : 4 input clock divider : 2 ? serial ports uart mode with brg : 1 synchronous/uart switchable mode with brg : 1 ? 10-bit a/d converter : 10 channels e2e1028-27-y5 this version: jan. 1998 previous version: nov. 1996
2/24 ? semiconductor MSM66507/66p507 ? transition detector : 6 ? watchdog timer : 1 ? interrupts nonmaskable : 1 maskable : internal 28/external 2 (4-level priority can be set) ? rom window function ? standby modes halt mode stop mode ? package 84-pin plastic qfj (plcc) (qfj84-p-s115-1.27-b) (product name: MSM66507- js-b) (product name: msm66p507- js-b) indicates the code number.
3/24 ? semiconductor MSM66507/66p507 block diagram p2.0/rto4 p2.5/rto9 p2.6/ftm10 p3.0/ftm11a p3.1/ftm11b p3.3/ftm11d p3.4/cap0 p3.7/cap3 p6.2/rxd1 p6.3/txd1 p6.4/rxc1 p6.5/txc1 p6.6/rxd0 p6.7/txd0 p7.4/pwm0 p7.7/pwm3 av dd v ref agnd ai0 ai9 p4.0/etmck p4.1/ectck p4.2/trns0 p4.7/trns5 p6.0/int0 p6.1/int1 nmi p7.3/clkout flexible timer serial port pwm a/d converter event timer transition detector interrupt peripheral wdt control registers cpu core ssp lrb psw pc memory control pointing r. local r. alu control acc, etc. instruction decoder system control ram 1.5k bytes rom 48k bytes ea ale psen rd /p7.1 wr /p7.0 wait/p7.2 ad0/p0.0 ad7/p0.7 a8/p1.0 a15/p1.7 port control osc0 osc1 res p0 p1 p2 p3 p4 p5 p6 p7 oe alu bus port control
4/24 ? semiconductor MSM66507/66p507 pin configuration (top view) 84-pin plastic qfj (plcc) 75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 trns4/p4.6 trns5/p4.7 p5.0 p5.1 p5.2 nmi res ea v dd av dd ai0 ai1 ai2 ai3 ai4 ai5 ai6 ai7 ai8 ai9 agnd 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p2.1/rto5 p2.0/rto4 oe p1.7/a15 p1.6/a14 p1.5/a13 p1.4/a12 p1.3/a11 p1.2/a10 p1.1/a9 p1.0/a8 v dd p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 p7.7/pwm3 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p4.5/trns3 p4.4/trns2 p4.3/trns1 p4.2/trns0 p4.1/ectck p4.0/etmck p3.7/cap3 p3.6/cap2 p3.5/cap1 p3.4/cap0 gnd p3.3/ftm11d p3.2/ftm11c p3.1/ftm11b p3.0/ftm11a p2.7 p2.6/ftm10 p2.5/rto9 p2.4/rto8 p2.3/rto7 p2.2/rto6 v ref int0/p6.0 int1/p6.1 rxd1/p6.2 txd1/p6.3 rxc1/p6.4 txc1/p6.5 rxd0/p6.6 txd0/p6.7 gnd osc0 osc1 ale psen wr /p7.0 rd /p7.1 wait/p7.2 clkout/p7.3 pwm0/p7.4 pwm1/p7.5 pwm2/p7.6
5/24 ? semiconductor MSM66507/66p507 pin description symbol type description p0.0-p0.7/ ad0-ad7 p0: 8-bit input-output port. each bit can be assigned to input or output. ad: when an external memory is used, these pins output the lower 8 bits of the address. these pins also input or output the data. i/o p1.0-p1.7/ a8-a15 p1: 8-bit input-output port. each bit can be assigned to input or output. a: when an external memory is used, these pins output the upper 8 bits of the address. i/o p2.0-p2.5/ rto4-rto9 p2.6/ftm10 p2.7 p2: 8-bit input-output port. each bit can be assigned to input or output. rto: output pin for real time output ftm10: capture input pin or real time output pin i/o p3.0-p3.3/ ftm11a-ftm11d p3.4-p3.7/ cap0-cap3 p3: 8-bit input-output port. each bit can be assigned to input or output. ftm11a: capture input pin or real time output pin ftm11b-d: 4-port real time output pin cap : capture input pin i/o p4.0/etmck p4.1/ectck p4.2-p4.7/ trns0-trns5 p4: 8-bit input-output port. each bit can be assigned to input or output. etmck: external clock input pin of 8-bit general timer ectck: external clock input pin of 8-bit event counter trns: transition detector input pin i/o p5.0-p5.2 p5: 3-bit input-output port. each bit can be assigned to input or output. i/o p6.0/int0 p6.1/int1 p6.2/rxd1 p6.3/txd1 p6.4/rxc1 p6.5/txc1 p6.6/rxd0 p6.7/txd0 p6: 8-bit input-output port. each bit can be assigned to input or output. int0, 1: external interrupt request input pin rxd1 : sci1 receiver data input pin txd1 : sci1 transmitter data output pin rxc1 : sci1 receiver circuit clock pin txc1 : sci1 transmitter circuit clock pin rxd0 : sci0 receiver data input pin txd0 : sci0 transmitter data output pin i/o p7.0/ wr p7.1/ rd p7.2/wait p7.3/clkout p7.4-p7.7/ pwm0-pwm3 p7: 8-bit input-output port. each bit can be assigned to input or output. wr : write strobe output pin for external data memory rd : road strobe output pin for external data memory wait: cpu wait request input pin when accessing external data memory clkout: output pin for supplying a clock to peripheral circuits pwm: pwm output pin i/o ai0-ai9 analog signal input only pin for a/d converter i av dd power supply input pin for a/d converter i v ref reference voltage input pin for a/d converter i agnd gnd input pin for a/d converter i osc0 basic clock oscillation pin i osc1 basic clock oscillation pin o
6/24 ? semiconductor MSM66507/66p507 pin description (continued) oe normally, when p0, p1, and p7.4-p7.7 are in an output state and the oe pin is "h" level, the ports go to a high impedance state. when oe pin is "l" level, the ports output "h" or "l" level. however, when p0, p1, and p7.4-p7.7 are in an input state, these ports are not under the influence of oe pin. i nmi nonmaskable interrupt request input pin i res reset input pin low-active reset input pin i ea normally set to "h" level. if set to "l" level, the program memory goes to external access mode and accesses external program memory. i v dd power supply pin i gnd ground pin i symbol type description psen strobe pulse output pin to fetch to external program memory o ale timing pulse output pin to latch the lower 8 bits of the address output from port 0 when the cpu accesses the external memory o
7/24 ? semiconductor MSM66507/66p507 registers accumulator control register (cr) program status word pointing register (pr) index register 1 index register 2 data pointer user stack pointer local register 15 0 acc psw bit 15 : carry flag (cy) bit 14 : zero flag (zf) bit 13 : half carry flag (hc) bit 12 : data descriptor (dd) bit 11 : sign flag (s) bit 10 : master interrupt priority flag (mip) bit 9 : overflow flag (ov) bit 8 : master interrupt enable flag (mie) bit 7-3 : user flag bit 2-0 : system control base 2-0 (scb2-0) pc lrb ssp 15 0 15 0 program counter local register base system stack pointer x1 x2 dp usp 15 0 er0 er1 er2 er3 r1 r3 r5 r7 r0 r2 r4 r6 7070
8/24 ? semiconductor MSM66507/66p507 sfr note: a i mark in the address column shows that there is a bit that does not exist in its register. * the initial values of prphf (sfr=18h) are as follows : when res pin is reset : vbff (bit 6) is set to "1" and ckout1 and 0 are set to "0". when reset by the wdt or brk instruction or by operation code trap : vbff (bit 6) keeps the value just before reset and ckout 1 and 0 are set to "0". in any cases, the state of the oe pin is read for oerd (bit 7). address [h] name symbol r/w reset 0000 system stack pointer ssp ff 0001 ff r/w 8/16-bit operation 0002 local register base 0003 lrbl lrbh undefined 0004 program status word 0005 pswl pswh 00 00 0006 accumlator 0007 accl acch 00 00 8/16 0010 rom window register romwin 00 0011 i ram ready control register ramrdy ff 0012 i rom ready control register romrdy ff 0014 stop code acceptor stpacp "0" 0015 i standby control register sbycon c8 0018 i peripheral control register prphf * 001c watchdog timer wdt halt 001d i tbc clock dividing counter tbckdvc f0 001e i tbc clock dividing register tbckdvr f0 0020 port 0 data register p0 00 0021 port 1 data register p1 00 0022 port 2 data register p2 00 0023 port 3 data register p3 00 0024 port 4 data register p4 00 0025 i port 5 data register p5 f8 0026 port 6 data register p6 00 0027 port 7 data register p7 00 0028 port 0 mode register p0io 00 0029 port 1 mode register p1io 00 002a port 2 mode register p2io 00 002b port 3 mode register p3io 00 002c port 4 mode register p4io 00 002d i port 5 mode register p5io f8 002e port 6 mode register p6io 00 002f port 7 mode register p7io 00 w r/w 8 w r r/w 8/16
9/24 ? semiconductor MSM66507/66p507 0031 port 1 secondary function control register p1sf 00 8 0032 i port 2 secondary function control register p2sf 80 8/16 0033 port 3 secondary function control register p3sf 00 0034 port 4 secondary function control register p4sf 00 8 0036 port 6 secondary function control register p6sf 00 8/16 0037 port 7 secondary function control register p7sf 00 0038 trns control register 0 trnscon0 00 0039 i trns control register 1 trnscon1 f0 c0 003a i transition detector trnsit 8 0040 interrupt request register 0 irq0l 00 8/16 0041 irq0h 00 0042 interrupt request register 1 irq1l 00 8 0044 interrupt enable register 0 ie0l 00 r/w 8/16 0045 ie0h 00 0046 interrupt enable register 1 ie1l 00 8 0048 interrupt request flag disable register 0 irqd0l 00 8/16 0049 irqd0h 00 004a interrupt request flag disable register 1 irqd1l 00 8 004e i nmi control register nmicon fc or 7c 8/16 004f i external interrupt control register exicon f0 0050 interrupt priority control register 00 ip00l 00 0051 ip00h 00 0052 ip01l 00 0053 ip01h 00 0054 interrupt priority control register 10 ip10l 00 8 0056 interrupt priority control register 11 ip11l 00 address [h] name symbol r/w reset 8/16-bit operation interrupt priority control register 01 sfr (continued) note: a i mark in the address column shows that there is a bit that does not exist in its register.
10/24 ? semiconductor MSM66507/66p507 0060 0061 sci0 timer register s0tmr 00 8 0062 i sci0 timer control register s0con 02 0063 i sci0 transmission control register st0con 82 0064 i sci0 reception control register sr0con 12 0065 0066 sci0 status register s0stat 00 r/w 8/16 0068 sci1 timer counter s1tm 00 0069 sci1 timer register s1tmr 00 006a i sci1 timer control register s1con 02 8 006b i 006c 006d 006e 0070 i gtmcon 30 0071 gevc 00 0072 8-bit general timer counter gtmc 00 0073 8/16 0080 pwr0 buffer register pw0bf 00 0081 00 0082 pwr1 buffer register 00 0083 00 0084 pwr2 buffer register pw2bf 00 0085 0086 00 0087 sci0 timer counter s0tm 8/16 00 sci0 transmission and reception buffer register s0buf undefined sci1 transmission control register st1con 80 sci1 reception control register sr1con 00 sci1 transmission and reception buffer register s1buf undefined sci1 status register s1stat 00 8-bit general timer control register 8-bit event counter 8-bit general timer register gtmr 00 00 00 pwr3 buffer register pw3bf pw1bf address [h] name symbol r/w reset 8/16-bit operation sfr (continued) note: a i mark in the address column shows that there is a bit that does not exist in its register.
11/24 ? semiconductor MSM66507/66p507 8 r/w 0098 pwm interrupt control register pwintcon 00 009a pwm control register 0 pwcon0 00 8/16 009b 009c 009d 009e i 009f i 00a0 tmr0 0000 00a1 00a2 timer register 1 tmr1 0000 00a3 00a4 00a5 00a6 00a7 00a8 00a9 00aa 00ab 00ac 00ad 00ae 16 00af 00b0 timer register 8 tmr8 00b1 0000 00b2 timer register 9 0000 00b3 00b4 timer register 10 tmr10 00b5 00b6 00b7 00b8 i 00b9 i 00ba i 00bb i 00bc 00bd i pwm control register 1 pwcon1 00 pwm clock counter pwdvc 00 pwm clock register pwdvr 00 pwm run register pwrun 30 timer register 0 0000 0000 timer register 11 tmr11 tmr9 pwm active register pwact f0 timer register 2 tmr2 0000 timer register 3 tmr3 0000 timer register 4 tmr4 0000 timer register 5 tmr5 0000 timer register 6 tmr6 0000 timer register 7 tmr7 0000 1f tmr0 lower 3-bit tmr0l 1f tmr1 lower 3-bit tmr1l 1f tmr2 lower 3-bit tmr2l 1f tmr3 lower 3-bit tmr3l 00 tm setting register tmsell f0 tmselh 8 8/16 address [h] name symbol r/w reset 8/16-bit operation sfr (continued) note: a i mark in the address column shows that there is a bit that does not exist in its register.
12/24 ? semiconductor MSM66507/66p507 00c0 tmr4 buffer register tmr4bf 00 00c1 00 r/w 00c2 tmr5 buffer register 00c3 tmr5bf 00c4 tmr6 buffer register 00c5 tmr6bf 00 00 00c6 tmr7 buffer register 00c7 tmr7bf 00 00 8/16 00c8 00c9 i 00ca 00cb 00cc 00cd 00ce 00cf i 00d0 i event control register evntconl 88 00d1 i evntconh 88 00d2 tmr mode register tmrmode 00 00d8 i event dividing counter 0 evdv0 c0 00d9 i 00da i 00db i event dividing counter 3 evdv3 c0 00dc i evdv0 buffer register evdv0bf c0 00dd i evdv1 buffer register evdv1bf c0 00de i 00df i evdv3 buffer register evdv3bf c0 00e0 a/dc result register 0 adcr0 undefined 00e1 a/dc result register 1 adcr1 00e2 a/dc result register 2 adcr2 00e3 a/dc result register 3 adcr3 00e4 a/dc result register 4 adcr4 00e5 a/dc result register 5 adcr5 00e6 a/dc result register 6 adcr6 00e7 a/dc result register 7 adcr7 00e8 a/dc result register 8 adcr8 00e9 a/dc result register 9 adcr9 00ea a/dc result register lower 0 ladcr0 00eb a/dc result register lower 1 ladcr1 00ec i a/dc result register lower 2 ladcr2 00ed i a/d interrupt control register adintcon f0 00ee i a/dc control register l adconl 80 8 8/16 r *8/16 00 00 timer control register tmcon 00 timer counter 0 lower 3-bit tm0l 1f timer counter 0 tm0 00 00 8 timer counter 1 tm1 00 00 capture control register 0 capcon0 00 capture control register 1 capcon1 f0 8/16 event dividing counter 1 evdv1 c0 event dividing counter 2 evdv2 c0 evdv2 buffer register evdv2bf c0 00ef i a/dc control register h adconh 80 r/w 8 address [h] name symbol r/w reset 8/16-bit operation sfr (continued) note: a i mark in the address column shows that there is a bit that does not exist in its register. * 8/16 means a special word manipulation. (for details, refer to the user's manual.)
13/24 ? semiconductor MSM66507/66p507 00f0 i rto control register 0 rtocon0 f8 00f1 i f8 r/w 00f2 i rto control register 2 00f3 i rtocon2 00f4 i rto control register 4 00f5 i rtocon4 fc fc 00f6 i rto control register 6 00f7 i rtocon6 f8 f8 8/16 00f8 00fe 00ff f8 f8 rto control register 8 rtocon8 00 8 emulator using area* rto control register 1 rtocon1 rto control register 3 rtocon3 rto control register 5 rtocon5 rto control register 7 rtocon7 address [h] name symbol r/w reset 8/16-bit operation sfr (continued) note: a i mark in the address column shows that there is a bit that does not exist in its register. * for the emulation using area, if the write is manipulated, the write data becomes invalid, and if the read is manipulated, the read data becomes undefined.
14/24 ? semiconductor MSM66507/66p507 1.2 page addressing a) sfr page b) fixed page c) current page addressing modes the MSM66507/66p507 provides independent 64k-byte data and 64k-byte program spaces with various types of addressing modes. these modes are shown below, for both ram (for data space) and rom (for program space). 1. ram addressing mode (for data space) 1.1 register addressing st a, fix 0c0h ram 0200h 02c0h example ror off 078h ram 00h 78 h example clr dir 780h ram 0700h 0780h example inc usp usp example la, sfr irq0 sfr 0000h 0040h example 1.3 direct data addressing
15/24 ? semiconductor MSM66507/66p507 1.4 pointing register indirect addressing a) dp/x1 indirect b) post increment dp indirect c) post decrement dp indirect d) dp/usp indirect with 7-bit displacement e) x1/x2 indirect with 16-bit base f) x1 indirect with 8-bit register (al, r0) displacement xchg a, [dp] ram dp example add a, [dp+] ram dp after access, dp is incremented by 2. example sub a, [dp-] ram dp after access, dp is decremented by 2. example and a, 12[dp] ram dp e64 to +63 example xor a, 1234h[x1] ram x1 0 to 65535 example or a, [x1+al] ram x1 al example
16/24 ? semiconductor MSM66507/66p507 b) current page sba area ( c0h to ffh) 2. rom addressing mode (for program space) 2.1 immediate addressing 2.2 table data addressing a) direct c) ram addressing indirect with 16-bit base b) ram addressing indirect 1.5 special bit area addressing a) fixed page sba area (02c0h to 02ffh) rb sbaoff 2e9h.7 ram c0h e9h example sb sbafix 2d1h.3 ram 02c0h 02d1h example lc a, 5678h rom 5678h example mov ssp, #7ffh rom address xxxxh example cmpc a, [usp] rom usp example lc a, 1234h[er0] rom er0 0 to 65535 ram example
17/24 ? semiconductor MSM66507/66p507 memory maps program memory space data memory space 0000h bfffh c000h ffffh 0000h 0049h 004ah 0069h 006ah 0fffh 1000h 17ffh 1800h bfffh internal rom area (48k bytes) external memory (16k bytes) vector table area (74 bytes) vcal table area (32 bytes) acal area (2k bytes) 0000h 00ffh 0100h 01ffh 0200h 02ffh 0300h 07ffh 0800h 09ffh 0a00h 0fffh 1000h ffffh sfr area reserved area fix area area where local register can be set area where rom window can be set 01ffh 0200h 0208h 0210h 0238h 0240h 0300h 02c0h x1 x2 dp usp x1 x2 dp usp x1 usp x1 x2 dp usp reserved area sba area (64 bytes) scb=0 scb=1 scb=7 pointing register set area where sb, rb, jbs, and jbr instructions can be accessed efficiently. internal ram area external memory area
18/24 ? semiconductor MSM66507/66p507 absolute maximum ratings recommended operating conditions digital power supply voltage analog power supply voltage analog reference voltage analog input voltage memory hold voltage operating frequency fan out v dd 4.5 to 5.5 av dd 4.5 to 5.5 v ref av dd C0.3 to av dd v v ai agnd to v ref v ddh 2.0 to 5.5 f osc 0 to 28 mhz n ttl load p0 p1 to p7 C40 to +85 c 20 2 1 f osc 24mhz v dd =av dd f osc =0hz ambient temperature ta f osc 24mhz mos load parameter symbol unit range condition ta=C40 to +85c 0 to 32 ta=C20 to +70c v dd =5v10% parameter symbol unit rating condition digital power supply voltage input voltage output voltage analog power supply voltage analog reference voltage analog input voltage power dissipation storage temperature v dd C0.3 to +7.0 ta=85c v i C0.3 to v dd +0.3 v o C0.3 to v dd +0.3 v av dd C0.3 to v dd +0.3 v ref C0.3 to av dd +0.3 v ai C0.3 to v ref p d gnd=agnd=0v per package per output 1300 mw 50 C50 to +150 c t stg (ta=25?c)
19/24 ? semiconductor MSM66507/66p507 *1. applied to p0 *2. applied to p1-p7 *3. applied to a in *4. applied to ale, psen *5. applied to res *6. applied to ea , oe , nmi *7. applied to osc0 *8. ports for input pins are v dd or gnd, otherwise no load. electrical characteristics dc characteristics parameter symbol unit condition min. typ max. h level input voltage h level input voltage h level input voltage v a a a a pf ma ma ma v ih v il v oh C C i o =C400ua i o =C200ua i o =3.2ma i o =1.6ma v i =v dd /0v v o =v dd /0v f=1mhz, ta=25?c v dd =2v, ta=25?c *8 f osc =24mhz no load *8 a/d in operation a/d stopped v o =2.4v C 2.2 v dd +0.3 (v dd =5v10%, ta=C40 to +85?c) C 0.80v dd v dd +0.3 C 0.85v dd v dd +0.3 C v dd C0.4 C C v dd C0.4 C C C2 C C C1 C C 10 C C 5 5 7 0.2 1 C C C C C 0.4 C C C C C C C C 0.4 1/C1 1/C250 15/C15 C C C C C C C C 25 C 55 C C C 2 4 10 10 60 130 100 C C0.3 0.8 C C0.3 0.2v dd C C0.3 0.15v dd *1 *2, 5, 6 *2, 5, 6 *7 *7 l level input voltage l level input voltage *1, 4 h level output voltage l level input voltage *2 h level output voltage i oh *1, 4 h level output current *2 *1, 4 *2 h level output current i ol i ref i lo c i c o l level output current input capacitance l level output current i dds i ddh output capacitance analog reference power supply voltage power consumption (in stop mode) power consumption (in halt mode) i dd power consumption *1, 2, 4 output leakage current v ol *1, 4 l level output voltage *2 l level output voltage *1 i ih /i il *5 *7 input leakage current input current input current *3, 6
20/24 ? semiconductor MSM66507/66p507 ac characteristics ? external program memory control ? external data memory control parameter symbol unit condition min. max. clock pulse width (osc) ale pulse width psen pusle width t ?w t aw t pw t pad t aas t aah c l =50pf ns t aad t aph t is t ih C 20.833 C 3t ?w C10 2t ?w C10 4t ?w C10 t ?w C5 t ?w C5 t ?w C0 t ?w C0 C C t ?w +10 t ?w +10 t ?w C10 C 0 35 t ?w +5 2t ?w +10 t ?w +5 psen pulse delay time low address setup time high address delay time low address hold time high address hold time instruction setup time instruction hold time (v dd =5v10%, ta=C40 to +85?c) parameter symbol unit condition min. max. clock pulse width (osc) ale pulse width rd pusle width t ?w t aw t rw t ww t rad t wad t aas t aah c l =50pf ns t aad t arh t ms t awh t mh t dd t dh C 20.833 C 3t ?w C10 t ?w C5 4t ?w C10 4t ?w C10 t ?w C0 t ?w C5 2t ?w C10 t ?w C5 t ?w C0 t ?w C0 C C 2t ?w +10 t ?w +10 t ?w C0 t ?w +10 t ?w +10 t ?w C0 t ?w +10 t ?w +10 t ?w C10 - 0 35 C t ?w +5 t ?w +5 t ?w +5 wr pulse width rd pulse delay time high address setup time wr pulse delay time high address hold time low address setup time low address hold time memory data setup time high address hold time memory data hold time data setup time data hold time (v dd =5v10%, ta=C40 to +85?c)
21/24 ? semiconductor MSM66507/66p507 clk t ?w t ?w ale psen ad 0-7 a 8-15 rd ad 0-7 a 8-15 wr ad 0-7 a 8-15 t aw t pad t pw t aah t aas t ih t is t rad t rw t wad t ww t aph t aad t aah t aas t mh t ms t arh t aad t aah t aas t dh t dd t awh t aad pc 0-7 inst 0-7 pc 8-15 rap 0-7 din 0-7 rap 8-15 rap 0-7 dout 0-7 rap 8-15
22/24 ? semiconductor MSM66507/66p507 reference voltage v ref av dd agnd ai 0-9 gnd 0v v dd +5v 47 w 0.1 f 0.1 f 47 f + 0.1 f 0.1f r i C + analog input 47 f + r i (analog input source impedance) 5k w < = a/d converter characteristics figure 1 recommended circuit parameter symbol unit condition min. typ. max. resolution refer to the recommended circuit (figure1). analog input source impedance r i 5k w t conv =512 f /ch refer to the measuring circuit (figure 2). by adtm set data f =1/f osc linearity error differential linearity error bit lsb s/ch n e l e d e zs e fs e ct t conv C C 10 C C3 C C 1 C 0 256 f +3 C C C3 C C C 1 768 f zero scale error full scale error conversion time crosstalk < = (av dd =v dd =v ref =5v10%, agnd=gnd=0v, ta=C40 to +85?c)
23/24 ? semiconductor MSM66507/66p507 definitions of terms 1. resolution the minimum distinguishable analog input value. for 10 bits, 2 10 =1024, i.e. (v ref Cagnd) ? 1024 2. linearity error the variance between the ideal conversion characteristics as a 10-bit a/d converter and the actual conversion characteristics. (quantized error is therefore not included.) 3. differential linearity error the smoothness of the conversion. the width of analog input voltage corresponding to the change by one bit of digital output is 1 lsb=(v ref Cagnd) ? 1024 ideally. the variance between this ideal bit size and bit size at arbitrary point in the conversion range. 4. zero scale error the variance between the ideal conversion characteristics at the switching point of digital output "000h to 001h" and actual conversion characteristics. 5. full scale error the variance between the ideal conversion characteristics at the switching point of digital output "3feh to 3ffh" and actual conversion characteristics. ai0 crosstalk is defined as the difference between the a/d conversion result when im- pressing the identical analog input to ai0-ai9 and the a/d conversion result in the circuit in the left figure. ai1 ai9 0.1f 5k w C + analog input v ref or agnd figure 2 crosstalk measuring circuit
24/24 ? semiconductor MSM66507/66p507 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfj84-p-s115-1.27-b package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 6.30 typ. mirror finish

▲Up To Search▲

Price & Availability of MSM66507

	To Download MSM66507 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .